(a) Field of the Invention
The present invention relates to a MOS transistor structure and, in particular, to a MOS transistor structure having three gate electrodes.
(b) Description of the Related Art
A conventional MOS transistor structure having three gate electrodes has been disclosed in “Threshold voltage adjusted-0.1 μm MOSFET using an inversed layer as very shallow source/drain” by H. Noda, F. Murai, and S. Kimura, IEDM Tech. Dig., 1993, pp. 123˜126.
Also, the U.S. Pat. Nos. 6,133,098 and 5,047,816 have been disclosed conventional MOS transistor fabrication techniques.
FIG. 1 shows a conventional MOS transistor structure having three gate electrodes. In case of NMOS, as shown in FIG. 1, a gate oxide layer 5 and a polysilicon main gate 8 doped with N-type impurity of high concentration are sequentially formed on a P-type silicon substrate 1.
Between sidewall gates 7 and the main gate 8, oxide layers 6 are formed so as to electrically isolate the sidewall gates 7 and the main gate 8 from each other, and the gate oxide layer 5 is between the sidewall gate 7 and the P-type silicon substrate 1.
A source 2 and a drain 3 are formed outward the sidewall gate 7 within the semiconductor substrate.
In case of PMOS, the entire structure is identical with the NMOS except for the conductive type of the impurity.
If a voltage is regularly applied to the above structure sidewall gates, the inversed layer below the sidewall gates acts as source/drain extension areas. In the meantime, if the voltage is applied to the main gate, a channel is formed such that the electric current flows from the drain to the source.
Since the sidewall gates are used for forming the virtual source/drain extension areas, the source/drain extension area can be formed at a junction depth of 5˜10 nm, thereby it is possible to efficiently improve a short channel effect such as a drain induced barrier lowering (DIBL) and a threshold voltage reduction effect which occurs by penetration of the drain electric field to the channel.
In case of forming the source/drain extension region through the conventional ion implantation process, however, the implanted impurity spreads into the channel region, thereby the source and drain are coupled if the gate length is below 0.06 μm. Even when the gate length is longer than 0.06 μm it is impossible to form the source/drain junction at the depth below 10 nm, resulting in occurrence of the severe short channel effect.
As an alternative to the technique for forming the source/drain extension region of the nano-transistor below 0.1 μm, a virtual source/drain extension region structure using the sidewall gates has been interested.
In order to regularly apply the voltage to the sidewall gates of the conventional MOS transistor structure having three gate electrodes, contacts should be formed at the sidewall gates, which is difficult. Also, the ions injected for the purpose to adjust the threshold voltage of the sidewall gates may spread in the following thermal treatment process so as to make an effect to the threshold voltage of the main gate region.
Furthermore, there can be parasitic capacitances between the sidewall gate and the main gate, between the sidewall gate and the body, and between the sidewall gate and the source/drain, that make slow the transfer speed of the sidewall gate bias voltage so as to degrade transistor performance.
Also, the voltage regularly applied to the sidewall gates causes additional leakage current so as to increase the power consumption and deteriorate the isolation layer between the sidewall gate and the main gate.